1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming various structures, such as conductive contacts and vias, on integrated circuit products.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements, such as transistors, capacitors, resistors, etc., to be formed on a given chip area according to a specified circuit layout. During the fabrication of complex integrated circuits using, for instance, MOS (Metal-Oxide-Semiconductor) technology, millions of transistors, e.g., N-channel transistors (NFETs) and/or P-channel transistors (PFETs), are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically includes doped source and drain regions that are formed in a semiconducting substrate and separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
Fabricating such circuit elements involves forming various “features” or “structures” of the devices, such as gate electrode structures, metal lines, conductive contacts, etc. Each of these features has a so-called “critical dimension,” which is typically the smallest size of a particular feature, e.g., the width of a line. As another example, for transistor devices, the critical dimension is gate length, which approximately corresponds to the width of the gate electrode that is positioned above the channel region of the device. Historically, such features and structures are typically formed by depositing a layer of material, forming a patterned photoresist mask layer above the layer of material and thereafter performing an etching process on the layer of material through the patterned photoresist mask layer, wherein the remaining portion of the layer of material after the etching process is the desired feature or structure. In other cases, a trench may be formed in a layer of material by performing an etching process through a patterned photoresist mask layer and thereafter a desired feature, e.g., a metal line, may be formed in the trench. The deposition, masking and etching techniques are performed using a variety of known deposition, etching and photolithography tools and techniques.
As should be clear from the foregoing, photolithography is one of the basic processes used in manufacturing integrated circuit products. At a very high level, photolithography involves (1) forming a layer of light or radiation-sensitive material, such as photoresist, above a layer of material or a substrate, (2) selectively exposing the radiation-sensitive material to a light generated by a light source (such as a DUV or EUV source) to transfer a pattern defined by a mask or reticle (interchangeable terms) to the radiation-sensitive material, and (3) developing the exposed layer of radiation-sensitive material to define a patterned mask layer. In general, the illuminated regions of the layer of photoresist material are chemically activated. In the case of a so-called “positive” resist mask, the exposed regions of the layer of photoresist material are subsequently removed in the developing process. In the case of a so-called “negative” resist mask, the illuminated regions of the layer of photoresist material are not removed during the developing process. Various process operations, such as etching or ion implantation processes, may then be performed on the underlying layer of material or substrate through the patterned photoresist mask layer.
Over the recent years and continuing to present day, there has been a constant demand for electrical consumer devices with improved operating characteristics, such as operating speed, and for physically smaller devices. As a result, device designers have reduced the physical size of the various features that are used in manufacturing integrated circuit devices to increase their performance capability and to produce smaller devices with more functionality, e.g., cell phones. To be more specific, the gate length of current generation transistor devices has been reduced to about 25-30 nm, and further reductions are contemplated in the future. Of course, the ultimate goal in integrated circuit fabrication is to faithfully reproduce the original circuit design on the integrated circuit product. Historically, the feature sizes and pitches (spacing between features) employed in integrated circuit products were such that a desired pattern could be formed using a single patterned photoresist masking layer. However, in recent years, device dimensions and pitches have been reduced to the point where existing photolithography tools, e.g., 193 nm wavelength photolithography tools, cannot form single patterned mask layers with all of the features of the overall target pattern.
To overcome the limitations of current day photolithography tools and techniques, the semiconductor manufacturing industry has developed and employed several so-called double patterning techniques to be able to manufacture devices with features sizes that are smaller than can be patterned using a single exposure photolithography process. Double patterning generally involves the formation and use of two separate patterned photoresist mask layers instead of one to form the desired feature. Using these techniques, the second mask must be accurately aligned with the first mask. Two examples of known double patterning techniques include a so-called LELE (Litho-Etch-Litho-Etch) process and a LFLE (Litho-Freeze-Litho-Etch) process. However, such double patterning techniques are expensive and add to processing complexity.
The present disclosure is directed to various methods of forming various structures, such as conductive contacts and vias, on integrated circuit products that may solve or at least reduce some of the problems identified above.